1. Field of the Invention
The present invention relates to test mode features for integrated circuits. More particularly, the present invention relates scan path test mode features for synchronous and pipelined memories.
2. Background
It has become increasingly important to build test circuitry into integrated circuits. Scan path and Built-In Self-Test (BIST) techniques have been developed to verify the proper logic function of integrated circuits, and are valuable tools for testing the logical operation of circuits within an integrated circuit. These techniques have also been used to test or monitor the state of circuit nodes that may be otherwise inaccessible from external pins of the integrated device.
Some logic failures may be due to internal timing problems or skews within a device. If these timings can be altered, a previously inoperative part may be fixed or altered to function correctly. Additionally, the function of particular circuits or the entire integrated circuit may be characterized in response to adjusting timing parameters within the device. It also may be advantageous to adjust internal timing parameters to increase the speed of a particular circuit or the overall response of the integrated circuit. Current scan path and BIST techniques, however, are not conventionally used to programmably alter the internal timing of circuits. Therefore, what is needed is a means for altering the internal timing of signals of circuits to more accurately determine the cause of failures within the device, to improve characterization of circuit or device responses, or to increase (or decrease) the response of a device.
Scan path and BIST techniques have also been used in memory devices such as asynchronous static random access memory (SRAM) devices to test the integrity of the memory core. Synchronous SRAMs, and especially synchronous pipelined SRAMs, present particularly difficult problems of test observability and characterization. FIG. 1 shows a conventional synchronous pipelined SRAM 100 having an asynchronous memory core 104, clocked input register 102, and clocked output register 106. Data or address information is clocked into input register 102, and is subsequently provided to memory core 104. Similarly, data output from memory core 104 is clocked into and out of register 106.
When testing memory core 104, only the output of output register 106 can be monitored. Output register 106 prevents the observation of (or "masks") internal memory signal transients from memory core 104. If memory core 104 is malfunctioning, then it is possible that output register 106 could mask this error by erroneously outputting expected data. Therefore, it may be difficult to determine whether output register 106 or memory core 104 is defective.
Therefore, what is needed is a means for disabling the clocked output register in a synchronous SRAM device to increase the test observability of the memory core, to directly monitor signals output by memory core 104, and/or to increase the likelihood of determining whether failures are being caused by defective memory locations or by the clocked output register.
Synchronous or pipelined memories often use clock signals for timing certain functions associated with the memory core. Incorrectly designed, manufactured, or margined time settings in these clock signals may cause failures to be observed at output register 106 even though the memory core itself is functioning properly. For example, if a sense amplifier circuit is prematurely enabled to read out data from the memory core, output register 106 may clock out incorrect data.
Therefore, what is needed is a means to disable output register 106 to monitor directly the effects of internal clock signals on the memory core. What is also needed is a means to alter the timing of internal clock signals to determine whether any failures are the result of improper signal timing or a defective memory core.